Our goal is to propose VLSI architectures specific to the numerical algorithms concerning the signal and image processing. This research cannot be accomplished without an expertise of the algorithms and architecture of arithmetic processing as well in fixed and floating point representations.
To quickly study the performances of various architectures, we propose an original design environment and synthesis CAD tool allowing to develop generators of numerical components with a high level of generics and abstraction.
In this context, we develop :
- a library of arithmetic operators generators ArithLib
- a Stochastic Floating-Point Unit (SFPU) based on Discrete Stochastic Arithmetic (DSA) allowing to control and estimate rounding errors in floating-point computations
- numerical filter generators to study the performances of various architectures for time-frequency representation of high-frequency signals.
- a synthesis tool using redundant arithmetic to optimize numerical datapaths
