Physical Design And Development of 3D Stacked Tree-based FPGA

Introduction

 Three-dimensional integrated circuits (3D ICs) are attractive options for overcoming the barriers in interconnect scaling and performance. Three-dimensional integration is an emerging technology that is expected to lead to an industry paradigm shift due to its tremendous benefits. The 3D integration technologies has enabled the semiconductor industry to design and manufacture, highly integrated systems by vertically stacking and connecting various materials, technologies and functional components together. The main aim of LIP6 3D Tree-based FPGA is to improve the performance and density drastically to maintain the overall pace according to Moore’s law. The project stages includes an experimental research, develop 3D physical design using Tezzaron 130nm Design Kit, simulate and validate 3D-stacks and test various demonstrators to develop practical methods for 3D design and manufacturing, to build high density and high performance 3D Tree-based FPGA.

Architecture under Consideration

The main focus of the internship is to study the issues associated with 2D physical design methods and develop solutions to design 3D Tree-based FPGA architecture to improve density, speed, interconnect performance.

 

 

Fig1 : A representation of 3D Tree-based FPGA infrastructure

 

The Tree-based FPGA architecture, is based on butterfly Fat Tree style interconnect. The main motivation for the 3D Tree-based FPGA is to achieve the best performance by using 3D vertical interconnect technology(TSVs). Tree-based FPGA is a hierarchical tree whose leaves are logic blocks. It has linear populated switch boxes and unidirectional wires. The downward network based on the Butterfly Fat Tree topology, involve a logarithmic population growth of unidirectional switch blocks. The upward network connect the outputs of the logic block to different levels of downward network using BFT like distribution.

 

 

 

Fig2. Tree-based FPGA Interconnect : 2 level upward and downwrad programmable interconnect network.

 

The logic blocks can be organized into k size clusters and interconnects organized into different levels. The upward and downward networks are designed in way to give maximum flexibility to all logic blocks inputs and outputs to reach the top level and back to any of the leafs.

Internship Focus: Design and Development of 3D Stacked FPGA

The main focus areas of 3D Tree-based FPGA is to develop 3D physical design :

1. Architecture Study
2. 3D Implementation (Such as Placement, Optimization, Routing etc
3. Physical Design and TSV aware 3D floorplanning:- 3D DRC/LVS, Timing, Power, Signal and clock integrity
4. 3D Parameter extraction and verification

Requirements

Physical Design experience, knowledge of Layout tools etc 

 

Supervision

Professor Habib Mehrez (Habib.Mehrez@lip6.fr)

Dr Zied Marrakchi(zied.marrakchi@lip6.fr)

Vinod Pangracious(vinod.pangracious@lip6.fr)

 

Reference

• Z. Marrakchi, H. Mrabet, U. Farooq, and H. Mehrez, FPGA Interconnect Topologies Exploration, in International Journalof Reconfigurable Computing, vol. 15, Nov. 2009, pp. 795–825.

• Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez. Efficient tree topology for FPGA interconnect network, ACM Great Lakes Symposium on VLSI pp, 321-326, 2008. 

• V. Pangracious, Z. Marrakchi, E. Amouri, and H. Mehrez, Performance Analysis and Optimization of High Density Tree-based 3D Multilevel FPGA, in ARC 2013, Accepted for publication,vol. 25, 2013, pp. 197–203.

• V. Pangracious, H. Mehrez, E. Amouri, and Z. Marrakchi, Physical Design Exploration of 3D Tree-based FPGA Architecture, in GLSVLSI 2013, Accepted for publication., vol. 2, May 2013,pp. 229–230.